The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor device having reduced contact resistance.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as field effect transistors (FETs) and on-chip capacitors, are fabricated on a single wafer. Some non-planar device architectures, such as vertical field effect transistors (VFETs), employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. A typical VFET device includes a vertical fin or nanowire that extends upward from the substrate. The fin or nanowire forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, and the gate is disposed on one or more of the fin or nanowire sidewalls.